True Sharing and False Sharing
True Sharing & False Sharing Computer systems with multiple multicore processors are becoming more popular with the evolution of technology. These systems have independent L1 and L2 cache but shared memory. The interconnect can connect all the processors directly to the main memory. While working with shared memory systems, we see both true and false sharing. In this article, we will discuss both these topics in detail. True Sharing True sharing happens when multiple cores access the same variable on the same cache line. Example Assuming we have a cache line of 2 words. Core0 and core1 are modifying the same address in the memory, let's say 0xA00. Since the cache line is of 2 words, both core0 and core1 cores will load the address from 0xA00 – 0xA08 in their caches. When core0 modifies the address, it invalidates its cache line along with the core1 cache line and vice versa. What if core0 has stored something on the variable and needs to load it back, bu...